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| GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Rev. 01 -- 11 May 2004 Product data 1. Description The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance (100 mA/12 ) with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation. The device is configured as two 8-bit transceivers that share a common clock and a master output enable pin, but also have individual latch timing and output enable signals. D-type flip-flops and D-type latches enable three modes of data transfer; Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The combination of reduced output swing, reduced input threshold levels and configurable edge control provides the higher speed operation of GTL/GTL+ backplanes. The GTL1655 can be used at GTL (VTT = 1.2 V, VREF = 0.8 V) or GTL+ (VTT = 1.5 V, VREF = 1.0 V) signalling levels. Port A and the control inputs are compliant with LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or GTL+ signal levels, with VREF providing the reference voltage input. The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA) and the clock pin (CP) are used to control the data flow through the two 8-bit transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be controlled. The OE pin can be used to disable all of the I/O pins. To optimize signal integrity, the GTL1655 features an adjustable edge rate control (VERC). By adjusting VERC between GND and VCC, a designer can adjust the Port B edge rate to suit an application's load conditions. The GTL1655 permits true live insertion capability by incorporating: * BIAS VCC, to pre-charge outputs and avoid disturbing active data during card insertion. * Ioff to disable current flow through powered-off I/Os. * Power-up 3-state, which ensures outputs are high-impedance during power-up, thus preventing bus contention issues. Once VCC is above 1.5 V, the power-up 3-state circuit relinquishes control of the outputs to the OE pin. To ensure the outputs remain 3-state, the OE pin should be tied to VCC via a pull-up resistor. Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 2. Features s Combination of D-type latches and D-type flip-flops for transceiver operation in clocked, latched or transparent mode s Logic level translation between LVTTL and GTL/GTL+ signals s HIGH-drive LOW-output-impedance (100 mA/12 ) on Port B s Configurable rise and fall times on Port B s Supports live insertion (Ioff, Power-up 3-state, and BIAS VCC) s Bus Hold on Port A inputs s Over voltage tolerance on Port A s Minimized switching noise through use of distributed VCC and GND pins s Available in TSSOP64 package s Industrial temperature range (-40 C to +85 C) s ESD protection x HBM EIA/JESD22-A114-A exceeds 2000 V x CDM EIA/JESD22-C101 exceeds 1000 V s Latch-up EIA/JEDS78 exceeds 200 mA 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns Symbol tPLH Parameter propagation delay, nAn to nBn Conditions VCC = 3.3 V; VERC = GND; VTT = 1.5 V; VREF = 1 V VCC = 3.3 V; VERC = GND; VTT = 1.5 V; VREF = 1 V propagation delay, nBn to nAn tPHL propagation delay, nAn to nBn VCC = 3.3 V VCC = 3.3 V; VERC = GND; VTT = 1.5 V; VREF = 1 V VCC = 3.3 V; VERC = GND; VTT = 1.5 V; VREF = 1 V propagation delay, nBn to nAn Ci CI/O input capacitance (control pins) I/O capacitance, Port A I/O capacitance, Port B VCC = 3.3 V Vi = VCC or GND Vi = VCC or GND Vi = VCC or GND Min Typ 3.9 4.4 2.6 3.1 2.7 4.2 3 7 8 Max Unit ns ns ns ns ns ns pF pF pF 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 2 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 4. Ordering information Table 2: Ordering information Package Name Description Version SOT646-1 Type number GTL1655DGG TSSOP64 plastic thin shrink small outline package; 64 leads; body width 6.1 mm Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. 4.1 Ordering options Table 3: Part marking Topside mark GTL1655DGG Temperature range Tamb = -40 C to +85 C Type number GTL1655DGG 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 3 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 5. Pinning information 5.1 Pinning 1OEAB 1OEBA VCC 1A1 GND 1A2 1A3 GND 1A4 1 2 3 4 5 6 7 8 9 64 CP 63 1LEAB 62 1LEBA 61 VERC 60 GND 59 1B1 58 1B2 57 GND 56 1B3 55 1B4 54 1B5 53 GND 52 1B6 51 1B7 50 VCC 49 1B8 48 2B1 47 GND 46 2B2 45 2B3 44 GND 43 2B4 42 2B5 41 VREF 40 2B6 39 GND 38 2B7 37 2B8 36 BIAS_VCC 35 2LEAB 34 2LEBA 33 OE 002aaa763 GND 10 1A5 11 GND 12 1A6 13 1A7 14 VCC 15 1A8 16 2A1 17 GND 18 2A2 19 2A3 20 GND 21 2A4 22 2A5 23 GND 24 2A6 25 GND 26 2A7 27 VCC 28 2A8 29 GND 30 2OEAB 31 2OEBA 32 GTL1655DGG Fig 1. TSSOP64 pin configuration. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 4 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 5.2 Pin description Table 4: Symbol 1OEAB 1OEBA VCC 1A1 to 1A8 GND Pin description Pin 1 2 3, 15, 28, 50 Description output enable 1A-to-1B (active-LOW) output enable 1B-to-1A (active-LOW) DC supply voltage 4, 6, 7, 9, 11, 13, data inputs/outputs port 1A 14, 16 5, 8, 10, 12, 18, 21, 24, 26, 30, 39, 44, 47, 53, 57, 60 17, 19, 20, 22, 23, 25, 27, 29 31 32 33 34 35 36 37, 38, 40, 42, 43, 45, 46, 48 41 49, 51, 52, 54, 55, 56, 58, 59 61 62 63 64 ground (0 V) 2A1 to 2A8 2OEAB 2OEBA OE 2LEBA 2LEAB BIAS_VCC 2B8 to 2B1 VREF 1B8 to 1B1 VERC 1LEBA 1LEAB CP data inputs/outputs port 2A output enable 2A-to-2B (active-LOW) output enable 2B-to-2A (active-LOW) output enable, all I/O pins (active-LOW) latch enable 2B-to-2A latch enable 2A-to-2B bias supply voltage data inputs/outputs port 2B reference voltage data inputs/outputs port 1B edge-rate control voltage Port B latch enable 2B-to-2A latch enable 1A-to-1B clock input 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 5 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 6. Functional description 41 61 VREF VERC CP 64 1LEAB 63 1LEBA 1OEBA 1OEAB OE 1A1 62 2 1 33 4 1D C1 CP 1D C1 CP 59 1B1 TO 7 OTHER CHANNELS 002aaa764 Fig 2. Logic diagram. VREF VERC CP 41 61 64 2LEAB 35 2LEBA 2OEBA 2OEAB OE 2A1 34 32 31 33 17 1D C1 CP 1D C1 CP 48 2B1 TO 7 OTHER CHANNELS 002aaa765 Fig 3. Logic diagram. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 6 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 6.1 Function table Table 5: Function table See Table note [1]. Inputs OEAB H L L L L L L LEAB X H H L L L L CP X X X H L Port A X L H L H X X Output Port B Z L H L H B0[2] B0[3] isolation transparent transparent registered registered previous state previous state Mode Table 6: Output Enable function table See Table note [1]. Inputs OE L L L L H OEAB L L H H X OEBA L H L H X Outputs Port A active Z active Z Z Port B active active Z Z Z Table 7: Port B edge-rate control (VERC) function table See Table note [1]. Input VERC Logic level H L [1] Output port B edge-rate Nominal voltage VCC GND slow fast [2] [3] A-to-B data flow is shown. B-to-A is similar, but uses OEBA, LEBA, and CP. It is not recommended to set OEAB and OEBA LOW at the same time. X -- don't care H -- HIGH voltage level L -- LOW voltage level Z -- high-impedance OFF-state -- LOW-to-HIGH transition Output level before the indicated steady-state input conditions were established, provided that CP was HIGH before LEAB went LOW. Output level before the indicated steady-state input conditions were established. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 7 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 7. Limiting values Table 8: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). See Table note [1] and Table note [2] Symbol VCC BIAS VCC IIK Vi Vo Parameter DC supply voltage BIAS supply voltage input clamping diode current DC input voltage DC output voltage Vi < 0 V port A port B; VERC, VREF output in HIGH or power-OFF state; port A output in HIGH or power-OFF state; port B IOL(d) IOH(d) Tstg [1] [3] [3] Conditions Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -65 Max +4.6 +4.6 -50 +7.0 +4.6 +7.0 +4.6 48 200 48 +150 Unit V V mA V V V V mA mA mA C DC LOW-level diode output current DC HIGH-level diode output current storage temperature port A port B port A [2] [3] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Section 8 "Recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 8 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 8. Recommended operating conditions Table 9: Symbol BIAS VCC VTT VREF Vi VIH Recommended operating conditions Parameter DC supply voltage termination voltage GTL reference voltage input voltage HIGH-level input voltage GTL GTL+ GTL GTL+ port B except port B port B except port B VERC VIL LOW-level input voltage port B except port B VERC |IIK| IOH IOL t/VCC Tamb input clamp current HIGH-level output current LOW-level output current power-up ramp rate operating ambient temperature port A port A port B Conditions Min 3.0 1.14 1.35 0.74 0.87 0 0 VREF + 50 mV 2.0 VCC - 0.6 200 -40 Max 3.6 1.26 1.65 0.87 1.10 VTT 5.5 VREF - 50 mV 0.8 0.6 18 -24 24 100 85 Unit V V V V V V V V V V V V V mA mA mA mA s/V C 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 9 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 9. Static characteristics Table 10: DC characteristics Tamb = -40 C to +85 C; values otherwise stated VREF = 1 V; VTT = 1.5 V. Symbol VIK VOH Parameter input clamp voltage HIGH-level output voltage Conditions VCC = 3.0 V; IIK = 19 mA port A VCC = 3.0 V to 3.6 V; IOH = -100 A VCC = 3.0 V; IOH = -12 mA VCC = 3.0 V; IOH = -24 mA VOL LOW-level output voltage port A VCC = 3.0 to 3.6 V; IOL = 100 A VCC = 3.0 V; IOL = 12 mA VCC = 3.0 V; IOL = 24 mA port B VCC = 3.0 V; IOL = 40 mA VCC = 3.0 V; IOL = 80 mA VCC = 3.0 V; IOL = 100 mA Ii input leakage current control pins port B Ioff output OFF current port A + control pin port B IHOLD bus hold current, A outputs port A VCC = 3.6 V; Vi = VCC or GND VCC = 3.6 V; Vi = VTT or GND VCC = 0 V; Vo = 0 V to 3.6 V VCC = 0 V; Vo = 0 V to 1.5 V VCC = 3.0 V; Vi = 0.8 V VCC = 3.0 V; Vi = 2.0 V overdrive current IOZH IOZL IOZ IOZPU IOZPD HIGH OFF-state output current LOW OFF-state output current OFF-state output current power-up 3-state output current power-down 3-state output current port A port B port B port A VCC = 3.6 V; Vi = 0 V to VCC VCC = 3.6 V; Vo = 1.5 V VCC = 3.6 V; Vo = 0.4 V VCC = 3.6 V; Vo = VCC or GND [3] [2] Min - Typ[1] - Max -1.2 0.2 0.4 0.55 0.2 0.4 0.5 10 10 100 300 500 10 -10 10 50 50 Unit V V V V V V V V V V A A A A A A A A A A A A VCC - 0.2 2.4 2.2 75 -75 - VCC = 0 to 3.6 V; Vo = 0.5 V to 3 V; OE = LOW VCC = 3.6 to 0 V; Vo = 0.5 V to 3 V; OE = LOW 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 10 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Table 10: DC characteristics...continued Tamb = -40 C to +85 C; values otherwise stated VREF = 1 V; VTT = 1.5 V. Symbol ICC Parameter quiescent supply current Conditions outputs HIGH outputs LOW disabled VCC = 3.6 V; Vi = VCC or GND; Io = 0 mA VCC = 3.6 V; Vi = VCC or GND; Io = 0 mA VCC = 3.6 V; Vi = VCC or GND; Io = 0 mA [4] Min - Typ[1] - Max 45 Unit mA - - 45 mA - - 45 mA ICC additional quiescent supply current per input pin; except port B input capacitance I/O capacitance VCC = 3.6 V; one input at VCC - 0.6 V; port A or control inputs at VCC or GN D control pins port A port B VCC = 3.6 V; Vi = VCC or 0 VCC = 3.6 V; Vi = VCC or 0 VCC = 3.6 V; Vi = VCC or 0 - 0.1 - mA Ci CIO - 3 7 8 5 8 10 pF pF pF [1] [2] [3] [4] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, this parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Table 11: Live insertion characteristics Tamb = -40 C to +85 C Symbol ICC (BIAS VCC) Parameter supply current Conditions VCC = 0 V to 3.0 V; V (port B) = 0 to 1.2 V; Vi (BIAS VCC) = 3.0 V to 3.6 V VCC = 3.0 V to 3.6 V; V (port B) = 0 to 1.2 V; Vi (BIAS VCC) = 3.0 V to 3.6 V Vo Io output voltage output current port B port B VCC = 0 V; Vi (BIAS VCC) = 3.3 V VCC = 0 V; V (port B) = 0.4 V; Vi (BIAS VCC) = 3 V to 3.6 V VCC = 0 V to 3.6 V; OE = 3.3 V; V (port B) = 0 V to 1.5 V VCC = 0 V to 1.5 V; OE = 0 V to 3.3 V; V (port B) = 0 V to 1.5 V Min Typ Max 5 10 Unit mA A 1 -1 - - 1.2 300 300 V A A A 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 11 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 10. Dynamic characteristics Table 12: Timing requirements over recommended supply voltage VTT = 1.2 V; VREF = 0.8 V and VERC = VCC or GND for GTL (unless otherwise noted; see Figures 15 and 16). Tamb = -40 C to +85 C. Symbol tW tsu th Parameter pulse duration set-up time hold time Conditions CP HIGH or LOW; see Figures 4 and 5 LE HIGH; see Figures 6 and 7 data before CP; see Figures 4 and 5 data before LE; see Figures 6 and 7 data after CP; see Figures 4 and 5 data after LE; see Figures 6 and 7 Table 13: Port A to Port B switching VTT = 1.2 V; VREF = 0.8 V and VERC = VCC or GND for GTL (see Figure 16). Tamb = -40 C to +85 C. Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL V/t tsk(o) output slew rate output edge skew OEAB or OE to B LEAB to B CP to B A to B OEAB or OE to B LEAB to B CP to B Parameter A to B Conditions OEAB = OE = 0 V; LEAB = 3 V OEAB = OE = 0 V; LEAB = 0 V OEAB = OE = 0 V; CP = 0 or 3 V LEAB = 3.0 V; Port A = 0 V OEAB = OE = 0 V; LEAB = 3 V OEAB = OE = 0 V; LEAB = 0 V OEAB = OE = 0 V; CP = 0 or 3 V LEAB = 3.0 V; Port A = 0 V 0.6 V to 1.0 V measured at VREF VERC = VCC; see Figure 10 VERC = VCC; see Figure 4 VERC = VCC; see Figure 8 VERC = VCC; see Figure 12 VERC = GND; see Figure 10 VERC = GND; see Figure 4 VERC = GND; see Figure 8 VERC = GND; see Figure 12 VERC = VCC VERC = GND Min 3.1 2.2 3.4 2.4 3.3 2.6 2.7 2.5 2.3 1.7 2.7 1.8 2.5 2.0 2.0 2.0 Typ 5.3 3.8 5.9 4.1 5.7 4.6 5.3 3.9 4.4 2.7 5.2 3.7 4.8 3.6 4.8 3.1 Max 6.2 6.2 7.2 6.0 7.0 6.8 6.5 6.4 5.3 4.4 6.1 5.3 6.5 5.3 6.2 4.9 1 1 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns V/ns V/ns ns Min 3.0 3.0 2.7 2.8 0.4 1.2 Typ Max Unit ns ns ns ns ns ns 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 12 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Table 14: Port B to Port A switching VTT = 1.2 V; VREF = 0.8 V for GTL (see Figure 15). Tamb = -40 C to +85 C. Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZL tPLZ tPZH tPHZ tsk(o) output edge skew OEBA or OE to A LEBA = 3.0 V; Port B = 0 V LEBA = 3 V; Port B = VTT measured at 1.5 V see Figure 13 see Figure 14 LEBA to A CP to A Parameter maximum frequency B to A OEBA = OE = 0 V; LEBA = 3 V OEBA = OE = 0 V; LEBA = 0 V OEBA = OE = 0 V see Figure 11 see Figure 5 see Figure 9 Conditions Min 160 1.8 2.3 1.5 1.5 1.3 1.4 1.3 1.7 1.3 1.7 Typ 2.6 4.2 3.1 3.7 2.7 3.1 3.1 2.8 3.3 3.3 Max 4.9 5.3 4.4 4.6 4.0 3.9 5.1 6.1 5.1 6.1 1 Unit MHz ns ns ns ns ns ns ns ns ns ns ns 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 13 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Table 15: Timing requirements over recommended supply voltage VTT = 1.5 V; VREF = 1 V and VERC = VCC or GND for GTL+ (unless otherwise noted). Tamb = -40 C to +85 C. Symbol tW tsu th Parameter pulse duration set-up time hold time Conditions CP HIGH or LOW; see Figures 4 and 5 LE HIGH; see Figures 6 and 7 data before CP; see Figures 4 and 5 data before LE; see Figures 6 and 7 data after CP; see Figures 4 and 5 data after LE; see Figures 6 and 7 Table 16: Port A to Port B switching VTT = 1.5 V; VREF = 1 V and VERC = VCC or GND for GTL+ (see Figures 15 and 16). Tamb = -40 C to +85 C. Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL V/t tsk(o) output slew rate output edge skew OEAB or OE to B LEAB to B CP to B A to B OEAB or OE to B LEAB to B CP to B Parameter A to B Conditions OEAB = OE = 0 V; LEAB = 3 V OEAB = OE = 0 V; LEAB = 0 V OEAB = OE = 0 V; CP = 0 or 3 V LEAB = 3.0 V; Port A = 0 V OEAB = OE = 0 V; LEAB = 3 V OEAB = OE = 0 V; LEAB = 0 V OEAB = OE = 0 V; CP = 0 or 3 V LEAB = 3.0 V; Port A = 0 V 0.6 V to 1.3 V measured at VREF VERC = VCC; see Figure 10 VERC = VCC; see Figure 4 VERC = VCC; see Figure 8 VERC = VCC; see Figure 12 VERC = GND; see Figure 10 VERC = GND; see Figure 4 VERC = GND; see Figure 8 VERC = GND; see Figure 12 VERC = VCC VERC = GND Min 3.0 2.3 3.3 2.7 3.2 2.8 3.2 2.6 2.3 1.7 2.5 1.9 2.5 2.1 2.1 2.0 Typ 4.7 4.4 5.3 4.7 5.2 5.2 4.8 4.6 3.9 3.1 4.8 4.1 4.3 4.0 4.4 3.4 Max 6.1 6.5 7.0 6.2 6.8 7.1 6.5 6.6 5.2 4.5 6.0 5.4 6.5 5.4 6.1 5.0 1 1 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns V/ns V/ns ns Min 3.0 3.0 2.7 2.8 0.4 1.2 Typ Max Unit ns ns ns ns ns ns 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 14 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Table 17: Port B to Port A switching VTT = 1.5 V; VREF = 1 V for GTL+ (see Figures 15 and 16). Tamb = -40 C to +85 C. Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZL tPLZ tPZH tPHZ tsk(o) output edge skew OEBA or OE to A LEBA = 3.0 V; Port B = 0 V LEBA = 3 V; Port B = VTT measured at 1.5 V see Figure 13 see Figure 14 LEBA to A CP to A Parameter maximum frequency B to A OEBA = OE = 0 V; LEBA = 3 V OEBA = OE = 0 V; LEBA = 0 V OEBA = OE = 0 V see Figure 11 see Figure 5 see Figure 9 Conditions Min 160 1.8 2.3 1.5 1.5 1.3 1.4 1.3 1.7 1.3 1.7 Typ 2.6 4.2 3.1 3.7 2.7 3.1 3.1 2.8 3.3 3.3 Max 4.9 5.3 4.4 4.6 4.0 3.9 5.1 6.1 5.1 6.1 1 Unit MHz ns ns ns ns ns ns ns ns ns ns ns 10.1 AC waveforms 3.0 V 1.5 V tsu CP input 1.5 V 1.5 V tsu 1.5 V 0V th 3.0 V 1.5 V tW tPLH Port B output VREF 1.5 V tW 1.5 V 0V tPHL VTT VREF VOL 002aaa766 002aaa767 Port A input Port B input VTT VREF tsu VREF VREF tsu VREF 0V th 3.0 V 1.5 V 0V tW tPHL VOH 1.5 V VOL th th 1.5 V tW tPLH 1.5 V CP input Port A output 1.5 V Test condition: OEAB = OE = 0 V Test condition: OEAB = OE = 0 V; LEBA = 0 V Fig 4. CP to B timing. 3.0 V 1.5 V tsu LEAB input 1.5 V 1.5 V tsu 1.5 V 0V th 3.0 V 1.5 V 1.5 V tW 1.5 V 0V 002aaa768 Fig 5. CP to A timing. VTT VREF tsu LEBA input VREF VREF tsu VREF 0V th 3.0 V 1.5 V 1.5 V tW 1.5 V 0V 002aaa769 Port A input Port B input th th Test condition: OEAB = OE = 0 V Test condition: OEAB = OE = 0 V Fig 6. LEAB set-up and hold times. Fig 7. LEBA set-up and hold times. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 15 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 3.0 V LEAB input 1.5 V tPLH Port B output VREF 1.5 V tW 1.5 V 0V tPHL VTT VREF VOL 002aaa770 002aaa771 3.0 V LEBA input 1.5 V tPLH Port A output 1.5 V 1.5 V tW 1.5 V 0V tPHL VOH 1.5 V VOL Test condition: OEAB = OE = 0 V; CP = 0 V or 3 V Test condition: OEAB = OE = 0 V; CP = 0 V or 3 V Fig 8. LEAB to B propagation delay. 3.0 V Port A input 1.5 V tPLH Port B input VREF 1.5 V 0V tPHL VTT VREF VOL 002aaa772 Fig 9. LEBA to A propagation delay. VTT VREF tPLH Port A input 1.5 V VREF 0V tPHL VOH 1.5 V VOL 002aaa773 Port B input Test conditions: OEAB = OE = 0 V; LEAB = 3 V Test conditions: OEBA = OE = 0 V; LEBA = 3 V Fig 10. A to B propagation delay. 3.0 V 1.5 V tPHL Port B output VREF 1.5 V 0V tPLH VTT VREF VOL 002aaa774 Fig 11. B to A propagation delay. OE or OEBA input 3.0 V 1.5 V tPZL Port A output 1.5 V 1.5 V 0V tPLZ 3.0 V VOL + 0.3 V 002aaa775 OE or OEAB input VOL Test conditions: LEAB = 3 V; Port A = 0 V Test conditions: LEBA = 3 V; Port B = 0 V Fig 12. OE or OEAB to B propagation delay. OE or OEBA input Fig 13. OE or OEBA to A propagation delay. 3.0 V 1.5 V tPZH 1.5 V 0V tPHZ VOH - 0.3 V VOH 0V 002aaa776 Port A output 1.5 V Test conditions: LEBA = 3 V; Port B = VTT Fig 14. OE or OEBA to A propagation delay. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 16 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 11. Test information S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 500 002aaa777 VO RL 500 6V open GND RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance ZO of the pulse generator. Fig 15. Load circuitry for Port A output switching times. VTT VCC PULSE GENERATOR VI D.U.T. RT CL 30 pF 002aaa778 VO RL 12.5 RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance ZO of the pulse generator. Fig 16. Load circuitry for Port B output switching times. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 17 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 12. Package outline TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1 D E A X c y HE vMA Z 64 33 A2 A1 pin 1 index Lp L 1 bp 32 wM detail X (A 3) A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.27 0.17 c 0.2 0.1 D (1) 17.1 16.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.1 Z 0.89 0.61 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT646-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 00-08-21 03-02-18 Fig 17. TSSOP64 package outline (SOT646-1). 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 18 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended. 13.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 19 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 13.5 Package related soldering information Table 18: Package[1] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, USON, VFBGA Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable Reflow[2] suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4] HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[8], [1] [2] suitable not recommended[5][6] not recommended[7] WQCCN..L[8] not suitable suitable suitable suitable not suitable PMFP[9], For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12936 Product data Rev. 01 -- 11 May 2004 20 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. [3] [4] [5] [6] [7] [8] [9] 14. Revision history Table 19: Rev Date 01 20040511 Revision history CPCN Description Product data (9397 750 12936). 9397 750 12936 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 21 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion 15. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 12936 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 -- 11 May 2004 22 of 23 Philips Semiconductors GTL1655 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion Contents 1 2 3 4 4.1 5 5.1 5.2 6 6.1 7 8 9 10 10.1 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 12 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 20 Package related soldering information . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 (c) Koninklijke Philips Electronics N.V. 2004. Printed in the U.S.A. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 11 May 2004 Document order number: 9397 750 12936 |
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